The architecture of a conventional flash memory array is known in the art. Generally, a memory array includes a number of lines arranged as rows and columns. The rows of the array are commonly referred to as word lines and the columns as bit lines. The word lines and bit lines overlap at what can be referred to as nodes. Situated at or near each node is a memory cell, which is generally some type of transistor. In a virtual ground architecture, a bit line can serve as either a source or drain line for the transistor (memory cell), depending on which memory cell is being program verified or read.
A typical flash memory cell includes a substrate in which source and drain regions have been formed, and a gate element formed on the substrate in proximity to the source and drain regions. The gate element typically includes a floating gate and a control gate separated by an oxide-nitride-oxide (ONO) layer. The gate element and the substrate (specifically, the source and drain regions in the substrate) are typically separated by a tunnel oxide layer that consists of silicon dioxide.
While conventional memory cells perform satisfactorily, it is desirable to scale them down in size so that a greater number of memory cells can be put into a given area. Furthermore, increasing the density of memory cells is expected to increase the speed at which the memory array operates.
Accordingly, a device and/or method that increases the density of memory cells in a memory array would be of value. The present invention provides this and other advantages.